The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for effective validation of execution units within a processor.
A flow of instruction execution of a computer program may be determined by branch instructions. The various paths taken in the course of the instruction execution determine the result of the program. Conditional branches, which are dependent upon results of previous instructions to determine the result of the condition, are bottlenecks in the program execution. Speculative execution, branch target buffer, branch prediction table, or the like, are just some of the micro-architectural features introduced to overcome such bottlenecks. Verifying the functionality of a branch unit and its allied micro-architectural features and architectural correctness of the processor in conjunction with these micro-architectural features plays a central role in post-silicon validation. Currently, the algorithms used for such validation deal with only static patterns. One disadvantage with static branch pattern test generation is a failure to stress the branch unit to the extreme since the branch path is predetermined and will not change during every re-execution of the same test case. Further, modern day processors have added numerous advanced features to the branch unit, such as a local predictor table, a global predictor table, and a global history vector, all of which can be stressed only with varying branch patterns in a test case.